NVIDIA uses AI to design GPU: the latest H100 has been used, which reduces the chip area by 25% compared with traditional EDA

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NVIDIA finally revealed ：

H100 It's actually close 13000 Circuits , yes AI The design of the ？！

In the latest paper , They introduced how to use deep reinforcement learning agent Method of designing circuit .

According to the researchers , This method is also the first in the industry .

It is worth mentioning that , This article includes references , Only short 6 page .

Many netizens expressed that , It was so cool, ！

Learn to build circuit frames by playing games

As Moore's law slows down , Developing other technologies to improve chip performance has become increasingly important .

Smaller design 、 faster 、 Arithmetic circuits with lower power consumption , Is one of the ways .

Based on this background , The researchers proposed PrefixRL—— Optimize Parallel Prefix Circuits with deep reinforcement learning .

According to the researchers , They not only proved AI You can design circuits from scratch , And ratio EDA The tool is designed smaller 、 faster .

Latest NVIDIA Hopper Architecture has 13000 individual AI Examples of circuit design .

Let's take a look at this study .

This paper mainly studies a popular parallel prefix circuit , Two characteristics of the circuit are emphatically discussed ： Circuit area and delay .

Existing basic optimization ideas , It uses a circuit generator to convert prefix graphics into circuits with wires and logic gates , And then use the physical synthesis tool to further optimize .

They regard arithmetic circuit design as a reinforcement learning task , Train one agent To optimize two features .

For Prefix Circuits , Also designed an environment .

In this environment agent Play building circuit architecture （ Prefix graphics ） The game of , You can add or Delete node , You will be rewarded for minimizing circuit area and low delay .

Used by researchers Q-Learning Algorithms to train agent.

First, the prefix graph is represented as a grid , Every element in the grid is mapped to a node in the circuit .

Both input and output are grids , Only each element in the input grid indicates whether the node exists , The output of each element represents the... Used to add or remove nodes Q value .

In actual training ,PrefixRL It is a highly computational task ： Physical simulation of each GPU need 256 individual CPU, Training 64b Use cases cost more than 32000 individual GPU Hours .

So , Researchers have also developed a distributed reinforcement learning training platform Raptor.

Results show , At the same delay 、 Under efficiency PrefixRL Area ratio of adder EDA The area of the tool adder is reduced 25%.

Research team

This research is from NVIDIA applied deep learning research group .

They hope this method will make AI Applied to practical circuit design problems .

In recent years ,AI Many technology companies are already working on designing chips .

The most typical example is Google , last year 6 Month in Nature Published an article on ：A graph placement methodology for fast chip design.

The paper said ,AI Can be in 6 Generate chip design drawings within hours , And better than human design .

And Samsung 、 New ideas 、cadence And other enterprises also have corresponding solutions .

A while ago in NVIDIA GTC At the conference , Chief scientist 、 Master of computer architecture Bill Dally Just share AI Several applications in chip design .

Including predicted voltage drop 、 Predict parasitic parameters 、 Layout and wiring 、 Automated standard cell migration .

however , Even if progress is frequent , There are also many voices of doubt , such as , The design ability is even worse than that of human beings .

about AI Designing chips , What do you think ？

Reference link ：
[1]https://developer.nvidia.com/blog/designing-arithmetic-circuits-with-deep-reinforcement-learning/
[2]https://arxiv.org/pdf/2205.07000.pdf
[3]https://twitter.com/rjrshr/status/1545446397759016962
[4]https://www.hpcwire.com/2022/04/18/nvidia-rd-chief-on-how-ai-is-improving-chip-design/